Concurrency-aware compiler optimizations for hardware description languages
Abstract
In this article, we discuss the application of compiler technology for eliminating redundant computation in hardware simulation. We discuss how concurrency in hardware description languages (HDLs) presents opportunities for expression reuse across different threads. While accounting for discrete event simulation semantics, we extend the data flow analysis framework to concurrent threads. In this process, we introduce a rewriting scheme named ∂VF and a graph representation to model sensitivity relationships among threads. An algorithm for identifying common sub-expressions as applied to HDLs is presented. Related issues, such as scheduling correctness, are also considered.
Research Areas
