I received a Ph.D. in Computer Engineering from Purdue University at West-Lafayette, IN, working with Jose Fortes and Rudolf Eigenmann on Processing-In-Memory (PIM) hardware-software codesign designing both a novel microarchitecture and compiler optimizations in 2004. From 2005 to 2009 I worked as an Assistant Professor in Electrical and Computer Engineering, at the University of Calgary, Canada. I created the Multi-threaded Architecture Lab. with research on computer micro-architecture, performance and compiler optimizations, and database and distributed systems. From 2010 to 2013 I worked at Intel Corporation Santa Clara, CA., working on binary translation, performance and compiler optimizations, microarchitecture, performance monitoring, and computer security. In 2002, I interned at Hewlett-Packard in Palo Alto, CA where I worked on performance profiling tools. I received an M.Sc., from Colorado State University in Electrical and Computer Engineering in 1997 working on computer security. From 1997 to 1999, I worked for Cypress Semiconductors doing firmware and hardware design, while studying at Stanford University computer architecture and VLSI design.
ISMM in conjunction with PLDI 2016, ACM
Analyzing and enhancing the parallel sort operation on multithreaded architectures
The Journal of Supercomputing, vol. 53 (2010), pp. 293-312