Full-Chip Simulations, Keys to Success
Venue
SNUG Silicon Valley 2015 Proceedings, Silicon Valley
Publication Year
2015
Authors
BibTeX
Abstract
As designs continue to grow larger and ever more complex, full-chip simulations
remain a critical component of design verification. These simulations pose a unique
set of challenges that require different approaches than those used at the block or
sub-chip level. This paper defines the key goals of full-chip simulations and
outlines guiding principles to follow when developing a new environment. Special
attention is paid to architecting for speed, both speed of simulation as well as
speed of debug. Lessons learned over the years along with specific recommendations
are presented.
