Concurrency-aware compiler optimizations for hardware description languages
Venue
ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. Volume 18, Issue 1 (2013), 10:1-10:16
Publication Year
2013
Authors
Harikumar Somakumar
BibTeX
Abstract
In this article, we discuss the application of compiler technology for eliminating
redundant computation in hardware simulation. We discuss how concurrency in
hardware description languages (HDLs) presents opportunities for expression reuse
across different threads. While accounting for discrete event simulation semantics,
we extend the data flow analysis framework to concurrent threads. In this process,
we introduce a rewriting scheme named ∂VF and a graph representation to model
sensitivity relationships among threads. An algorithm for identifying common
sub-expressions as applied to HDLs is presented. Related issues, such as scheduling
correctness, are also considered.
