Accelerator Compiler for the VENICE Vector Processor
Venue
FPGA, ACM (2012)
Publication Year
2012
Authors
Zhiduo Liu, Aaron Severance, Guy G.F. Lemieux, Satnam Singh
BibTeX
Abstract
This paper describes the compiler design for VENICE, a new soft vector processor
(SVP). The compiler is a new back-end target for Microsoft Accelerator, a
high-level data parallel library for C++ and C#. This allows us to automatically
compile high-level programs into VENICE assembly code, thus avoiding the process of
writing assembly code used by previous SVPs. Experimental results show the compiler
can generate scalable parallel code with execution times that are comparable to
hand-written VENICE assembly code. On data-parallel applications, VENICE at 100MHz
on an Altera DE3 platform runs at speeds comparable to one core of a 3.5GHz Intel
Xeon W3690 processor, beating it in performance on four of six benchmarks by up to
3.2%.
