Luiz André Barroso is a Distinguished Engineer at Google. His interests range from distributed system software infrastructure to the design of Google's computing platform. Prior to Google, Luiz was a member of the research staff at Digital Equipment Corporation and Compaq, where his group did some of the pioneering work on multi-core architectures. He has B.S. and M.S. degrees in Electrical Engineering from the Pontifícia Universidade Católica of Rio de Janeiro, and a Ph.D. in Computer Engineering from the University of Southern California.
“Power Management of Online Data-Intensive Services”, David Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber, Thomas F. Wenisch, Proceedings of the 38th ACM International Symposium on Computer Architecture, 2011.
[abstract] [pdf] [search]
“Warehouse-scale Computing: entering the teenage decade”, Luiz André Barroso, ACM Federated Computing Research Conference (2011).
[abstract] [dl.acm.org] [search]
“Availability in Globally Distributed Storage Systems”, Daniel Ford, Francois Labelle, Florentina Popovici, Murray Stokely, Van-Anh Truong, Luiz Barroso, Carrie Grimes, Sean Quinlan, Proceedings of the 9th USENIX Symposium on Operating Systems Design and Implementation, 2010.
[abstract] [pdf] [search]
“Dapper, a Large-Scale Distributed Systems Tracing Infrastructure”, Benjamin H. Sigelman, Luiz André Barroso, Mike Burrows, Pat Stephenson, Manoj Plakal, Donald Beaver, Saul Jaspan, Chandan Shanbhag, 2010.
[abstract] [research.google.com] [pdf] [search]
“Datacenter-scale Computing”, Luiz André Barroso, Parthasarathy Ranganathan, IEEE Micro, vol. 30 (2010), pp. 6-7.
[abstract] [computer.org] [search]
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, Luiz André Barroso, Urs Hölzle, 2009.
[abstract] [doi] [search]
“All Watts Considered”, Luiz Andre Barroso, Keynote address, International Symposium on Low Power Electronics and Design, 2007.
[doi.acm.org] [pdf] [search]
“Failure Trends in a Large Disk Drive Population”, Eduardo Pinheiro, Wolf-Dietrich Weber, Luiz André Barroso, 5th USENIX Conference on File and Storage Technologies (FAST 2007), pp. 17-29.
[abstract] [research.google.com] [search]
“Power Provisioning for a Warehouse-sized Computer”, Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso, The 34th ACM International Symposium on Computer Architecture, 2007.
[abstract] [research.google.com] [search]
“The Case for Energy-Proportional Computing”, Luiz André Barroso, Urs Hölzle, IEEE Computer, vol. 40 (2007).
[abstract] [computer.org] [pdf] [search]
“The Price of Performance: An Economic Case for Chip Multiprocessing”, Luiz Andre Barroso, ACM Queue, vol. 3 (2005), pp. 48-53.
[research.google.com] [pdf] [search]
“Web Search for a Planet: The Google Cluster Architecture”, Luiz Andre Barroso, Jeffrey Dean, Urs Hölzle, IEEE Micro, vol. 23 (2003), pp. 22-28.
[abstract] [research.google.com] [pdf] [search]
“Code layout optimizations for transaction processing workloads”, Alex Ramirez, Luiz André Barroso, Kourosh Gharachorloo, Robert Cohn, Josep Larriba-Pey, P. Geoffrey Lowney, Mateo Valero, ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, 2001, pp. 155-164.
[doi.acm.org] [search]
“Piranha: a scalable architecture based on single-chip multiprocessing”, Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese, ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture, 2000, pp. 282-293.
[doi.acm.org] [search]
“Memory system characterization of commercial workloads”, Luiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion, ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture, 1998, pp. 3-14.
[doi.acm.org] [search]
“Performance of database workloads on shared-memory systems with out-of-order processors”, Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso, ASPLOS-VIII: Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, 1998, pp. 307-318.
[doi.acm.org] [search]
“Design options for small-scale shared memory multiprocessors”, Luiz Andre Barroso, 1996.
[search]
“Performance Evaluation of the Slotted Ring Multiprocessor”, Michael Dubois, Luiz André Barroso, IEEE Trans. Comput., vol. 44 (1995), pp. 878-890.
[doi] [search]
“RPM: A Rapid Prototyping Engine for Multiprocessor Systems”, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois, Krishnan Ramamurthy, Computer, vol. 28 (1995), pp. 26-34.
[doi] [search]
“The design of RPM: an FPGA-based multiprocessor emulator”, Koray Öner, Luiz A. Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois, FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp. 60-66.
[doi.acm.org] [search]
“The performance of cache-coherent ring-based multiprocessors”, Luiz André Barroso, Michel Dubois, ISCA '93: Proceedings of the 20th annual international symposium on Computer architecture, 1993, pp. 268-277.
[doi.acm.org] [search]
“A methodology for performance evaluation of parallel applications on multiprocessors”, Daniel A. Menascé, Luiz André Barroso, J. Parallel Distrib. Comput., vol. 14 (1992), pp. 1-14.
[doi] [search]
“Scalability Problems in Multiprocessors with Private Caches”, Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner, PARLE '92: Proceedings of the 4th International PARLE Conference on Parallel Architectures and Languages Europe, 1992, pp. 211-230.
[search]
“Delayed consistency and its effects on the miss rate of parallel programs”, Michel Dubois, Jin Chin Wang, Luiz A. Barroso, Kangwoo Lee, Yung-Syau Chen, Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on Supercomputing, pp. 197-206.
[doi.acm.org] [search]