Kim Hazelwood

Kim Hazelwood's research interests broadly include performance analysis and hardware/software interaction (including computer architectures and compilers). Her specialties include dynamic binary translation and process virtualization. Since March 2012, Kim has been a member of the PIMPS team within the Platforms organization, where she is helping to steer the server roadmaps at Google by evaluating and analyzing the performance of important Google apps on next-generation systems. From August 2011 - March 2012, Kim was a member of the Gmail Client-Side Performance Team at Google, where she focused on tools and techniques for detecting and reducing the memory bloat of Javascript applications on browsers (e.g. Gmail on Chrome).

Kim joined Google after seven years on the computer science faculty at the University of Virginia, where she was promoted to Associate Professor with tenure in June 2011. While at UVa, she was also a one-day-per-week faculty consultant for Intel, where she helped co-develop the Pin dynamic instrumentation system, which has been downloaded over 60,000 times and cited in over 1000 publications.

Kim received her PhD at Harvard in 2004, where she worked under the direction of Michael Smith, who is now Dean of the Faculty of Arts & Sciences. She has over 40 publications, has authored one book, and is the recipient of numerous awards, including the Top 35 Innovators under 35, the Anita Borg Early Career Award, and the National Science Foundation Career Award.

Google Publications

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    Runtime adaptation: a case for reactive code alignment

    Michelle McDaniel, Kim Hazelwood

    Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era, ACM, New York, NY, USA (2012), pp. 1-11

Previous Publications

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    EcoSim: a language and experience teaching parallel programming in elementary school

    Chris Gregg, Luther Tychonievich, James Cohoon, Kim Hazelwood

    SIGCSE '12: Proceedings of the 43rd ACM technical symposium on Computer Science Education, ACM, New York, NY, USA (2012), pp. 51-56

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    Analyzing program flow within a many-kernel OpenCL application

    Perhaad Mistry, Chris Gregg, Norman Rubin, David Kaeli, Kim Hazelwood

    GPGPU-4: Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units, ACM, New York, NY, USA (2011), pp. 1-8

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    Dynamic Binary Modification: Tools, Techniques, and Applications

    Kim Hazelwood

    Morgan & Claypool Publishers (2011)

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    Finding cool code: An analysis of source-level causes of temperature effects

    Dan Upton, Kim Hazelwood

    ISPASS '11: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, IEEE Computer Society, Washington, DC, USA (2011), pp. 117-118

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    Performance characterization of mobile-class nodes: Why fewer bits is better

    Michelle McDaniel, Kim Hazelwood

    ISPASS '11: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, IEEE Computer Society, Washington, DC, USA (2011), pp. 131-132

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    Process-level virtualization for runtime adaptation of embedded software

    Kim Hazelwood

    DAC '11: Proceedings of the 48th Design Automation Conference, ACM, New York, NY, USA (2011), pp. 895-900

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    Where is the data? Why you cannot debate CPU vs. GPU performance without the answer

    Chris Gregg, Kim Hazelwood

    ISPASS '11: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, IEEE Computer Society, Washington, DC, USA (2011), pp. 134-144

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    Analyzing Parallel Programs with Pin

    Moshe (Maury) Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal

    Computer, vol. 43 (2010), pp. 34-41

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    Balancing memory and performance through selective flushing of software code caches

    Apala Guha, Kim Hazelwood, Mary Soffa

    CASES '10: Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems, ACM, New York, NY, USA, pp. 1-10

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    DBT path selection for holistic memory efficiency and performance

    Apala Guha, Kim hazelwood, Mary Lou Soffa

    VEE '10: Proceedings of the 6th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, ACM, New York, NY, USA (2010), pp. 145-156

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    Design of a custom VEE core in a chip multiprocessor

    Dan Upton, Kim Hazelwood

    SASP '10: Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors (SASP), IEEE Computer Society, Washington, DC, USA, pp. 97-100

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    Eliminating voltage emergencies via software-guided code transformations

    Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim Hazelwood

    ACM Trans. Archit. Code Optim., vol. 7 (2010), pp. 1-28

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    A cross-layer approach to heterogeneity and reliability

    Daniel Williams, Aprotim Sanyal, Dan Upton, Jason Mars, Sudeep Ghosh, Kim Hazelwood

    MEMOCODE'09: Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign, IEEE Press, Piscataway, NJ, USA (2009), pp. 88-97

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    Challenges and opportunities at all levels: interactions among operating systems, compilers, and multicore processors

    Kim Hazelwood, Mohamed Zahran

    SIGOPS Oper. Syst. Rev., vol. 43 (2009), pp. 3-4

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    Improving instrumentation speed via buffering

    Dan Upton, Kim Hazelwood, Robert Cohn, Greg Lueck

    WBIA '09: Proceedings of the Workshop on Binary Instrumentation and Applications, ACM, New York, NY, USA (2009), pp. 52-61

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    Scalable support for multithreaded applications on dynamic binary instrumentation systems

    Kim Hazelwood, Greg Lueck, Robert Cohn

    ISMM '09: Proceedings of the 2009 international symposium on Memory management, ACM, New York, NY, USA, pp. 20-29

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    Trace fragment selection within method-based JVMs

    Duane Merrill, Kim Hazelwood

    VEE '08: Proceedings of the fourth ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, ACM, New York, NY, USA (2008), pp. 41-50

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    Reducing exit stub memory consumption in code caches

    Apala Guha, Kim Hazelwood, Mary Lou Soffa

    HiPEAC'07: Proceedings of the 2nd international conference on High performance embedded architectures and compilers, Springer-Verlag, Berlin, Heidelberg (2007), pp. 87-101

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    SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance

    Steven Wallace, Kim Hazelwood

    CGO '07: Proceedings of the International Symposium on Code Generation and Optimization, IEEE Computer Society, Washington, DC, USA (2007), pp. 209-220

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    A Cross-Architectural Interface for Code Cache Manipulation

    Kim Hazelwood, Robert Cohn

    CGO '06: Proceedings of the International Symposium on Code Generation and Optimization, IEEE Computer Society, Washington, DC, USA (2006), pp. 17-27

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    A dynamic binary instrumentation engine for the ARM architecture

    Kim Hazelwood, Artur Klauser

    CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, ACM, New York, NY, USA, pp. 261-270

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    Managing bounded code caches in dynamic binary optimization systems

    Kim Hazelwood, Michael D. Smith

    ACM Trans. Archit. Code Optim., vol. 3 (2006), pp. 263-294

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    Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems

    Kim Hazelwood, James E. Smith

    CGO '04: Proceedings of the international symposium on Code generation and optimization, IEEE Computer Society, Washington, DC, USA (2004), pp. 89

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    Adaptive online context-sensitive inlining

    Kim Hazelwood, David Grove

    CGO '03: Proceedings of the international symposium on Code generation and optimization, IEEE Computer Society, Washington, DC, USA (2003), pp. 253-264

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    Code Cache Management Schemes for Dynamic Optimizers

    Kim Hazelwood, Michael D. Smith

    INTERACT '02: Proceedings of the Sixth Annual Workshop on Interaction between Compilers and Computer Architectures, IEEE Computer Society, Washington, DC, USA (2002), pp. 102

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    A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization

    Kim M. Hazelwood, Thomas M. Conte

    PACT '00: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, IEEE Computer Society, Washington, DC, USA, pp. 71